CLKS=10BIT, BURST=SWMODE, START=STOP, EDGE=RISING
A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
| SEL | Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,…, and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). |
| CLKDIV | The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. |
| BURST | Burst mode 0 (SWMODE): Software-controlled mode: Conversions are software-controlled and require 11 clocks. 1 (HWMODE): Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. |
| CLKS | This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). 0 (10BIT): 11 clocks / 10 bits 1 (9BIT): 10 clocks / 9 bits 2 (8BIT): 9 clocks / 8 bits 3 (7BIT): 8 clocks / 7 bits 4 (6BIT): 7 clocks / 6 bits 5 (5BIT): 6 clocks / 5 bits 6 (4BIT): 5 clocks / 4 bits 7 (3BIT): 4 clocks / 3 bits |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| START | When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 0 (STOP): No start (this value should be used when clearing PDN to 0). 1 (START): Start conversion now. 2 (EDGEPIO0_2): Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. 3 (EDGEPIO1_5): Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. 4 (EDGECT32B0_MAT0_1): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. 5 (EDGECT32B0_MAT1_1): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. 6 (EDGECT16B0_MAT0_1): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. 7 (EDGECT16B0_MAT1_1): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. |
| EDGE | This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal. 0 (RISING): Start conversion on a rising edge on the selected CAP/MAT signal. 1 (FALLING): Start conversion on a rising edge on the selected CAP/MAT signal. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |